Meta Off Campus 2026 Hiring Fresher For ASIC Engineer Intern | Bangalore

The ASIC Engineer Intern role at Meta is suitable for candidates looking to build experience in professional work environments, communication, teamwork, and business operations.

Meta builds technologies that help people connect, find communities, and grow businesses. Since the launch of Facebook in 2004, Meta has continuously transformed how people communicate. Platforms like Facebook, Instagram, Messenger, and WhatsApp now serve billions of users worldwide.

Meta’s engineering teams work on large-scale, cutting-edge systems, constantly pushing the limits of performance, efficiency, and sustainability. Joining Meta means working on impactful projects with world-class engineers.

Meta is looking for an ASIC Engineer Intern to join its Infrastructure organization. In this role, you will work on designing and verifying custom silicon accelerators used in Meta’s large-scale data centers. These accelerators power some of Meta’s most demanding workloads and help build energy-efficient (“Green”) data center solutions.

You’ll gain hands-on experience with advanced IPs and industry-standard tools while collaborating closely with experienced ASIC engineers.

• Develop tests, checkers, and coverage models to verify ASIC designs
• Understand design architecture and micro-architecture
• Write SystemVerilog / UVM / C code to generate test content
• Develop scripts to automate verification and validation processes
• Debug test failures and collaborate with design and modeling teams
• Improve verification processes and contribute to methodology enhancements

• Minimum Qualifications
• Currently pursuing or completed a Bachelor’s degree in:
• Electrical Engineering
• Computer Engineering
• Or related engineering fields
• Strong knowledge of Computer Architecture and Logic Design fundamentals
• Ability to think critically and solve verification problems creatively
• Must have valid work authorization in the country of employment
• Intention to return to degree program after internship completion
• Preferred Qualifications
• Pursuing or completed Master’s or PhD in relevant engineering fields
• Knowledge of SystemVerilog / Verilog / VHDL
• Scripting experience with Python or Perl

• Technical Skills
• Strong understanding of Digital Electronics and Logic Design
• Knowledge of Computer Architecture and Microarchitecture
• Basics of ASIC Design & Verification Flow
• Hands-on or academic experience with SystemVerilog / Verilog / VHDL
• Familiarity with UVM (Universal Verification Methodology) – basic to intermediate
• Programming knowledge in C / C++ for test generation
• Scripting skills using Python or Perl for automation
• Understanding of RTL Design, Simulation, and Debugging
• Exposure to EDA tools (Synopsys, Cadence, or similar) is a plus
• Analytical & Problem-Solving Skills
• Ability to debug complex design and verification issues
• Strong logical reasoning and attention to detail
• Capability to analyze test failures and suggest fixes
• Creative thinking to design effective verification strategies
• Soft Skills
• Good communication skills to collaborate with design and verification teams
• Ability to work in a team-oriented environment
• Willingness to learn new tools and technologies
• Strong time management and task prioritization skills

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